Methods and systems for system design automation (sda) of mixed signal electronic circuitry including embedded software designs

ABSTRACT

Methods and systems for SDA of mixed signal electronic circuitry including embedded software designs for creating ASICs, sub-systems, and SoCs. The SDA system described extends IP reuse beyond the circuit and stand-alone verification capabilities that are common practice today which limit the benefits of reuse. By solving the integration problem first in a loosely coupled manner, complex mixed signal SoC devices may achieve higher levels of IP reuse with push button ease through the cloud, significantly improving time to market, design resource limitations, risks for first time silicon success, and the tasks of managing business multiple relationships of IP providers. SDA generated designs use a multi-agent method of operation, creating powerful and flexible designs that provide both NOC (Network on a Chip) and NBC (Network Beyond the Chip) for distributed system operation, and enhanced non-intrusive in-system monitoring for mission critical and safety related applications.

CROSS REFERENCE TO RELATED APPLICATIONS

This application further claims the benefit of the following provisionalapplication which is here expressly incorporated by reference:

62/449,433 entitled “CLOUD BASED SERVICE FOR PERFORMING SYSTEM DESIGNAUTOMATION (SDA) OF MIXED SIGNAL WITH SOFTWARE DESIGNS,” filed on Jan.23, 2017 with Attorney Docket No. CONCOOlUSP;

Ser. No. 15/878,342 entitled “METHODS AND SYSTEMS FOR SYSTEM DESIGNAUTOMATION (SDA) OF MIXED SIGNAL ELECTRONIC CIRCUITRY INCLUDING EMBEDDEDSOFTWARE DESIGNS,” filed on Jan. 23, 2018 with Attorney Docket No.CONCOOlUSO; and

PCT/US18/14924 entitled “METHODS AND SYSTEMS FOR SYSTEM DESIGNAUTOMATION (SDA) OF MIXED SIGNAL ELECTRONIC CIRCUITRY INCLUDING EMBEDDEDSOFTWARE DESIGNS,” filed on Jan. 23, 2018 with Attorney Docket No.CONCOO1UWO.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to methods and systems for therapid development of ASIC, SoC, and sub-system designs for FPGA or mixedsignal silicon devices, including new devices incorporating embeddedsoftware functionality. More particularly, the present disclosureprovides methods and systems for system design automation (SDA) of mixedsignal electronic circuitry including embedded software designsaddressing needs for increased collaboration to deal with increasedcomplexities, including, but not limited to, cloud-basedimplementations.

BACKGROUND

The $400B semiconductor industry is dealing with unprecedenteddifficulties relating to the continued increased complexities of today'snew silicon. With devices including over 50M logic gates being common,and over 10% containing about 1B transistors, the human engineer'sability to understand all aspects of the SoC (System on Chip) beingdesigned are greatly diminished, if not over. System complexities arecreating an environment of unreasonable development schedules, costs,and risks. For example, a typical 20 nm new product may take years tobring to market, cost over $150M to develop, and be outdated beforereaching the required sale of over 10M units at $20 each to break even.Forecasts expect that by 2020, some parts will become 10 times morecomplex when reaching the 5 nm process node, with development costsexceeding $1B. As the limits of Moore's Law are reached, the problemsassociated with realizing increased system complexities continue to growas functionality extends beyond the boundaries of a monolithic deviceswith collaborative distributed system ecosystems.

These problems are creating difficulties in developing the newinnovative products required by OEM system developers, who instead arehaving to settle for older existing catalog parts. System designers mayno longer rely on silicon providers alone to address their SoC designneeds, and require new capabilities and tools to drive the successfuldevelopment of complex future ICs. The Electronic Design Automation(EDA) industry has delivered tremendous capabilities that have provencritical in bringing the semiconductor market to where it is today.Although EDA advancements have embraced and met the challenge to improvedesign productivity so that today's advanced processes may be utilized,together these advancements have now created a further need for SDAcapabilities.

Considering the present developments and growth in the SDA industry anumber of pressing needs have emerged. There are community needs bywhich SDA tools may provide essential interfaces to manage theintegration of all IC development flow tasks. These interfaces wouldallow full leveraging of SDA capabilities by flow development methods,as well as the added benefit of ensuring all stakeholders of an ICdevelopment flow may work together compatibly and more effectively.

Simplicity needs exist. System designers should be free from IC hardwareand/or software design burdens, as they seek to define and automatecomplex new SoC devices. Unlike EDA tools developed and used by ICdesign engineers, SDA tools need to focus primarily, but notexclusively, on system developer needs.

SDA tools also have reuse needs, including the efficient and effectivereuse of functional IP. IP reuse typically fails to solve the problem ofIP integration and verification. SDA tools need to provide for extendingIP reuse to the way that IP is used through all IC design flow aspects.In addition, for easy reuse, cleanly partitioned IP functions shoulddefine all required functionality though automation.

Architecture needs also exist. System automation requires standardizingthe way IP integrates together in a flexible and configurable manner.Architecture not only involves the circuitry required to physicallyconnect IP functions together, but also methods for defining, managing,and optimizing the required configurability of an inherently flexiblesystem.

Because SoCs may be very large and complex, needs exist for functionalmethods of bringing together communities of engineers and developers.Further, today's SDA engineering and design community seeks to delivercomplete functional SoC designs including both digital and analoghardware, as well as embedded and driver software. In so doing, theyconcentrate on solving all aspects of the way that various functions areintegrated, verified, and validated in a collaborative practicalfunctional SDA solution. Through these efforts, the resulting SDAsystems also provide a platform that manages various business aspects ofbuilding systems. These building systems include managing IP licensingfrom multiple vendors, including managing aspects of data, files, usesupport, bugs, licensing agreements, and auditing. These tasksfrequently discourage the adoption of IP from outside sources.

Now, more than at any previous time, the need exists for increasedcollaboration to deal with increased complexities. Collaborationprovides the only ways that customers, definers, decision makers,designers, manufacturers, and suppliers may work closer to ensureproject success. Installing new software tools may require laboriousevaluation and approvals, making it difficult to adopt new disruptivecapabilities. Acceleration capabilities may create unreasonable demandspikes on available infrastructure. Yet, security risks for increasedcollaboration necessitate a safe neutral ecosystem that remainsaccessible to all stakeholders. Properly addressing these growingconcerns becomes ever more necessary.

The IP market has been demonstrating 15-22% growth, with a forecast forcontinuing growth of about 18% over the next several years. But this iswithout the use of SDA capabilities. SDA further addresses, and evenremoves, some of the known barriers to IP reuse, further extending thebenefit of IP reuse to all aspects of the IC design flow. As such, SDAmay significantly increase the IP market Compound Annual Growth Rate(CAGR) to create and meet a significant untapped identified and growingmarket need.

Further, the pervasive use of Artificial Intelligence (AI) hardware andsoftware launches mankind into the dawn of a new era. System developersat the forefront of AI advancements are developing and deploying newcapabilities for interacting with an ever-evolving and random world.System design needs for automating autonomous tasks in collaborativelyworking with distributed systems emerge from future growing engineeringand design complexities. Many needs exist for SDA-based designs thatprovide a powerful and simple path to either interface or integrateMachine Learning (ML) and AI capabilities into scalable and flexibledesigns.

There are needs for SDA designs to offer developers maximum operationalflexibility. Mixed signal hardware and software IP must operate togetheras a multi-agent system, requiring no master controller to collaborate.Further, SDA-based designs must route data as necessary through theentire system, while providing all the ‘hooks’ necessary to providesystem observability, and adaptability. There are needs for SDA systemfeatures that make designs ‘AI-friendly,’ so that integration of ML andAI IP may be simply plugged into the system. Existing working systemoperation need to be monitored for ML, and behavior adapted, duringoperation using AI mixed signal IP tools. Additionally, input data fromother outside sources may also be observed for improved intelligentoperation. Today, no known standard system or approach satisfies theseincreasingly acute needs.

The time of intelligent adaptable distributed system operation is uponus. Old methods of operation and interoperability fall short. Today, theindustry demands a simple and efficient approach to automate systemdesign for the future.

BRIEF SUMMARY

The disclosed subject matter provides methods and systems for SDA ofmixed signal electronic circuitry including embedded software designs.

The present disclosed subject matter generally relates to SDAcapabilities or services for the rapid development of ASIC, SoC, andsub-system designs for FPGA or mixed signal silicon devices, includingnew devices incorporating embedded software functionality. In oneembodiment, the SDA flow is cloud-based and implemented in three phaseswhich require no special software or tools installed at the user orclient side:

Phase 1: Functional hardware or software module selection and toolselection and design with test bench automated build and verification

Phase 2: System Design User (SDU) use case definition and regressionsimulations

Phase 3: Final design optimization.

Using the SDA methods and systems here described, the SDU requires noexpert IC design knowledge to define, build, and simulate the desiredproduct from reused IP. The SDU may search, browse, and select desiredIP functionality much like any other common online shopping experience.A tabulating system indicates final design estimates as selections aremade for die size, pin count, IP license fees, total part cost, andother useful information. Once the functional selection process iscompleted, the SDU may automatically integrate and assemble the newdesign and corresponding simulation test bench at the push of a singlebutton. Within short order, automatic cloud-side mixed signal simulationfor integrated IP tool verification begins verifying the resultingdesign is properly operating, and indicates where possible problemsmight exist. The resulting design is highly flexible and configurablethrough defined parameters that define the manner IP is to worktogether, all controllable through a test bench debug port in simulationand/or other interfaces. Configuration of parameters for each IP controldata input source routing among the chip fabric, as well as mixed signalmode controls, and are all part of the cloud design database thatrelationally represents the specified design. Server-side simulationensures valuable IP implementation details may remain private, allowingan SDU to try before committing to license or buy mixed signal IP from3rd party developers.

Once the design and test bench are auto-built and auto-verified to beoperational, the SDU is ready to use the high-level verification testcase definer to specify how IP should be configured to work together toperform application specific targeted operational use cases. Since allaspects of the design are accessible through a database, test cases maybe defined through an intuitive easy to use web application where theSDU specifies test bench signal source conditions, data and signal eventrouting between IP tools, and IP mode control settings within thedesign.

SDUs are also able to define and manipulate test bench signal monitorsto set automatic pass/fail checks for the use case simulation. Theverification test case definer web application may use a variety ofmethods and views to aid SDUs in working with their custom design. Suchmethods and related tools may define operational requirement use casesthat become part of an overall regression for verification family oftest cases. These might include table manipulations, GUI drop boxselections, and/or schematic like graphic data flow representations, allworking through the database parameter definitions to manipulate thecollaborative nature of the system. Simulation efficient models are usedto validate the interoperable aspects of the final design, all whilecollecting operational metrics that may be used to further optimize andadjust the design if needed.

The last phase of SDA allows for the design to be optimized for thedefined use cases. Implemented assertion checks within the IP sockets,integration backbone, and test bench ensures problem areas areidentified and may be addressed. One example would include themonitoring and reporting of internal integration bus bandwidth use,allowing IP tools to be automatically partitioned into subsystems toaddress bandwidth issues.

A second example is identifying any possible missed data transfers andthe automatic adjustment of IP I/O FIFO depths to ensure data is notlost when the bus might remain busy for long periods of time. A thirdexample includes the automated analysis of verification test cases forthe utilized configuration states and optimizing the auto-builtintegration circuitry to include only the flexibility required by thefunctionally verified design.

Typically, multi-agent system operation has referred to software systemsolutions, and the presently disclosed SDA multi-agent architectureapplies to both HW and SW functional integration, even beyond physicalsemiconductor package boundaries. This makes the presently disclosedSDA-based designs useful for addressing the difficult aspects ofbuilding robust distributed systems. For example, a vehicle's AI ABSsubsystem might benefit from other vehicle AI galaxy sensor data,further interacting with an adaptive AI traffic control cluster, thateventually works together within a city corridor's super galaxy. In suchan example, it's clear that each level of AI must be able to workautonomously, yet collaboratively with its surrounding. Further, it mustbe able to be incrementally deployed and interact with all kinds ofrandom events.

A technical aspect of the present disclosure includes providing methodsand systems for SDA of mixed signal electronic circuitry includingembedded software designs for creating Application Specific IntegratedCircuits (ASICs), sub-systems, and SoCs. The SDA system describedextends IP reuse beyond the circuit and stand-alone verificationcapabilities that are common practice today which limit the benefits ofreuse. By solving the integration problem first in a loosely coupledmanner, complex mixed signal SoC devices may achieve higher levels of IPreuse with push button ease through the cloud, significantly improvingtime to market, design resource limitations, risks for first timesilicon success, and the tasks of managing business multiplerelationships of IP providers. SDA generated designs use a multi-agentmethod of operation, creating powerful and flexible designs that provideboth Network on a Chip (NOC) and Network Beyond the Chip (NBC) fordistributed system operation, and enhanced non-intrusive in-systemmonitoring for mission critical and safety related applications. Themethod of operation also eases integration of AI and ML functionality.

Another technical aspect of the present disclosure includes methods andsystems for SDA of mixed signal electronic circuitry including embeddedsoftware designs that enable the system developer to build and simulatenew designs in minutes using SDA. The disclosed subject matter providesprograms and/or scripts that automate the generation wrappers fromsystem integration database entries for mixed signal circuitry andsoftware IP tools. The presently disclosed methods and systems providemethods of operation able to present outputs in an identifiable mannerand implement configurable or fixed input select control circuitry orsoftware for tool inputs. From this derives assembling the tools as asystem through a NoC and software operating system (OS) implementation.The present disclosure, thus, provides programs and/or scripts thatcompile the generated design and test bench, and execute inheritedsimulation stimulus and self-checks from the IP tool containers. Note,however, that the presently disclosed IP modules do not necessarily needto be designed in a multi-agent loosely coupled operational manner, asthe wrapper takes care of this need for the IP function.

The disclosed configuration architecture allows this to be eitherinherited IP script or database driven. Here it is convenient tosystematically collect and store wrapper simulation data so that it maybe analyzed and drive database entry optimizations for a design based onthe way it's used in verification.

The disclosed subject matter also provides relational databasefunctionality. Here, mixed signal circuitry and/or software tool designfiles are organized, stored, as IP containers and accessed using aversion control system such as Git (/git/) in a usable form foraccomplishing SDA. This SDA system provides a common integration andmethod of use allowing systematic implementation for all aspects of IPreuse that may be represented in database form from the container, andworking with the relational database and code generators.

Yet a further technical aspect of the present disclosure includes asystem architecture whereby data and signals may flow between mixedsignal hardware or circuitry and/or software tools, which may beimplemented with IP source identifiers (source-based addresses,indexes). In this way, tool inputs may be obtained through configurationselects implemented in HW IP or SW IP wrappers, and further so thatconfiguration information may be represented in a relational databaseform. Configuration selects are implemented as system user configurableor fixed configuration settings from the database. Source identifiersmay be kept as absolute (unchanged) or relative (modified as it flowsthrough connected subsystems). Integrated operation is accomplished as a“configure input selects and let it work” manner. In other words,Functional IP may operate together in an integrated form without theneed of a typical central controller to control dataflow for the system,greatly simplifying the functional integration and automation buildproblem.

A yet further technical advantage of the presently disclosed subjectmatter includes the ability to support a cloud-based collaborativeenvironment. The subject matter here disclosed may be accomplish witheither a software installation, or via a cloud-based implementationwithout a software installation. Using a cloud-based shared environmentfor all stakeholders of a new design effort, the present SDA systemprovides a cloud-based IP tool for representing IP in a database formthat facilitates automation. The cloud-based IP tool here disclosedmanages all IPs owned/controlled by a user/group for design, support,and/or business management. The presently disclosed cloud based designtool enables defining a design and an associated test bench, includingthe IP that the design uses and the configuration of each of theemployed IP tools. Still further, the cloud-based environment hereprovided enables a cloud-based simulation tool for verifying circuitryand software mixed signal designs.

BRIEF DESCRIPTION OF THE DRAWINGS

The present subject matter will now be described in detail withreference to the drawings, which are provided as illustrative examplesof the subject matter so as to enable those skilled in the art topractice the subject matter. Notably, the FIGUREs and examples are notmeant to limit the scope of the present subject matter to a singleembodiment, but other embodiments are possible by way of interchange ofsome or all of the described or illustrated elements, that is, FIGUREsmay be somewhat simplified from showing all features that may beincluded in order to present the subject matter in a clearer manner,and, further, wherein:

FIG. 1 shows SDA cloud application partitioning according to theteachings of the present disclosure;

FIG. 2 shows an example design and test bench topology as heredisclosed;

FIGS. 3 through 5 show SDA applied to systems incorporating software IPas within the presently disclosed subject matter.

FIGS. 6 through 11 show database schema figures of operationalparameters as may be implemented in the present disclosure;

FIG. 12 shows the interfacing of industry functions with the describedSDA ecosystem according to the presently disclosed SDA system;

FIGS. 13 through 17 show web browser views of SDA access and use for usewith an exemplary embodiment of the present subject matter; and

FIG. 18 shows SDA subsystem bridging within the scope of the disclosedand claimed subject matter.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The detailed description set forth below in connection with the appendeddrawings is intended as a description of exemplary embodiments in whichthe presently disclosed process may be practiced. The term “exemplary”used throughout this description means “serving as an example, instance,or illustration,” and should not necessarily be construed as preferredor advantageous over other embodiments. The detailed descriptionincludes specific details for providing a thorough understanding of thepresently disclosed method and system. However, it will be apparent tothose skilled in the art that the presently disclosed process may bepracticed without these specific details. In some instances, well-knownstructures and devices are shown in block diagram form in order to avoidobscuring the concepts of the presently disclosed method and system.

In the present specification, an embodiment showing a singular componentshould not be considered limiting. Rather, the subject matter preferablyencompasses other embodiments including a plurality of the samecomponent, and vice-versa, unless explicitly stated otherwise herein.Moreover, applicants do not intend for any term in the specification orclaims to be ascribed an uncommon or special meaning unless explicitlyset forth as such. Further, the present subject matter encompassespresent and future known equivalents to the known components referred toherein by way of illustration.

Provided are novel methods and systems for SDA of mixed signalelectronic circuitry including embedded software designs for creatingASICs, SoCs, FPGA based designs, and subsystems. Reference will now bemade in detail to the example embodiment illustrated in the accompanyingdrawings. While the disclosed subject matter will be described inconjunction with the embodiment below, it will be understood that it isnot intended to limit the disclosed subject matter to this embodimentand examples.

On the contrary, the disclosed subject matter is intended to coveralternatives, modifications and equivalents, which may be includedwithin the spirit and scope of the disclosed subject matter as definedby the appended claims. Furthermore, in the following detaileddescription of the present disclosed subject matter, numerous specificdetails are set forth in order to more fully illustrate the presentdisclosed subject matter. However, it will be apparent to one ofordinary skill in the prior art that the present disclosed subjectmatter may be practiced without these specific details. In otherinstances, well-known methods and procedures, components and processeshave not been described in detail so as not to unnecessarily obscureaspects of the present disclosed subject matter.

It will, of course, be appreciated that in the development of any suchactual implementation, numerous implementation-specific decisions mustbe made to achieve the developer's specific goals, such as compliancewith application and business-related constraints, and that thesespecific goals will vary from one implementation to another and from onedeveloper to another. Moreover, it will be appreciated that such adevelopment effort might be complex and time-consuming, but wouldnevertheless be a routine undertaking of engineering for those ofordinary skill in the art having the benefit of this disclosure.

The method and system of the present disclosure enable the ability tobuild and simulate new mixed signal circuit and software designs inminutes. SDA simplifies and accelerates front-end chip development,expanding user base beyond expert designers so they may simply selectdesired IP functionality and begin system simulations with littleeffort. The presently disclosed methods and architecture for automatingthe earliest tasks provides practical and tangible benefits to allstakeholders through the entire development and product life cycle.

The SDA functions automate design and test bench builds, provide for IPreuse verification, and even integration optimization based on systemuse cases. The system of the present disclosure provides build designsand test benches that auto generate highly flexible and configurabledesigns. This includes IP wrappers, interconnect and buss fabric,documentation, test benches, and debug capability, all at the push of abutton.

The method and system of the present disclosure enable verifyingintegrated IP functions. By permitting auto verification of IP in anintegrated system form, and building a complete task-based mixed signalenvironment for the new system, users may begin building system-leveltargeted functional test-cases. The disclosed method and system alsoprovide a framework able to support flow for verification-driven designthat auto optimizes the integration of the design for the manner that IPis actually used together in a system, while including only theflexibility required or desired.

The presently disclosed method and system employs relational databasefunctionality and collaborative operational attributes that are managedthrough the relational database. In this construction, SDA efforts aredriven from the database. For instance, the present method and systemprovide inheritance functions where with a selected IP specification,configuration, and use requirements. Such inheritable functions from thePLAYERs IP library can be automatically used through the systemverification flow.

Here, system requirements may be managed through a scoreboard. Thesesystem requirements are captured so they may be bound to verificationtest cases. Specifications not critical to the design need may be markedas non-critical, driving further IP optimization decisions. Moreover,mixed signal test cases may be applied. Thus, mixed signal system testcases are built through database parameter control and auto generatedwhen simulated.

The method and system of the present disclosure includes unique systemarchitecture attributes. With the presently disclosed subject matter,system architecture provides object oriented-like IP integration, andhas been developed to facilitate automation. Here, integration overheadmay be managed and optimized through use of the relational database.

With the operational methods of the present disclosure, the task ofautomating the system IP components begins with a solution for solvingthe integration problem. Connectivity and configurable collaborativeinteroperability of IP needs are addressed, with them all parameterizedfor control through the database. In this context, SDA becomes flexibleand scalable. Here, SDA designs are built with clean IP partitioning,and are inherently flexible, scalable, and highly configurable. Here,too, SDA integration wrapper functionality may be easily optimized. Acollective design may be rapidly optimized through database attributes,or in system program configurations where required.

One aspect of the present disclosure includes a cloud-basedcollaborative environment, which establishes easy access to a presentlydisclosed shared SDA eco-system of the present disclosure. The sharedSDA eco-system helps to ensure that any stakeholder in a new design hasthe ability to quickly initiate and collaborate on new productdevelopment opportunities, in a highly functional and effective way.

With the presently disclosed method and system, there are no requiredsoftware installs. Preferably with a cloud-based platform, there is easyaccess to the present shared SDA eco-system. This access ensures thatany stakeholder in a new design has the ability to quickly initiate andcollaborate on new product development opportunities, in a highlyfunctional and effective way. At the same time, if a softwareinstallation is desired, such an installation may be effected to providethe presently disclosed novel functions and features, all within thescope of the present subject matter.

The presently disclosed SDA system includes AUDITION IP management tool,wherein new IP definitions, existing IP imports, user support, licenseand royalty management are all managed through a common web portal. TheSDA system provides ORCHESTRATE tool builds, whereby system definers mayshop and select desired IP to build and manage new designs. Moreover,the presently disclosed SDA system includes REHEARSE simulation andverification, including server side simulation utilizing inheritedconfiguration and operational tasks that are bound to projectrequirements for mixed signal targeted verification.

Another aspect of the presently disclosed SDA system includes a scalableinfrastructure whereby server side SDA capabilities may be easily scaledusing data center infrastructure. Open servers are available for ‘free’user exploration of available IP, including predefined subsystems anddefined designs looking for interest from other potential users. Inaddition, the SDA system provides business servers that are dedicatedfor the management of community business relationships, includingREHEARSE use, manufacturing audits, IP license agreements and usepayments, IP outsourcing, SDA portal customers, etc. The SDA system ofthe present disclosure provides REHEARSE servers, which are simulationservers for designs committed for simulation and verification services.

Yet another aspect of the presently disclosed novel SDA system includesa set of community access functions. The SDA system of the presentdisclosure includes an SDA dashboard that steers attention for IPproviders, definers, designers, customers, etc.) to where it isrequired, providing opportunities to manage effective workflows.

Community access functions further include controlled IP and designaccess functions, whereby owners may remain in control of IP visibility.These functions further permit control of what level (requirements,specs, documentation, users, support, simulation, source, etc.) ofaccess is desire, as well as providing options for sharing orcollaboration at all levels.

The SDA system provides a collaborative work environment in which allstakeholders for SDA work may share controlled access to aspects ofdefining, developing, and bringing a product to market. This measure ofsimplification enables participation beyond traditional roles and beyondorganizational boundaries, when desired.

The presently disclosed SDA system further includes SDA social mediafunctions. Through the SDA social media functions, a commoncollaborative portal offers the opportunity to mine new businessopportunities from IC customers, system developers, IP providers, andmanufacturers.

The SDA architecture of the present disclosure further includes IP reusemanagement functions. The SDA functions of the present disclosure solvean IP market integration and verification problem, thereby significantlyproviding more value. Delivering SDA through the cloud, as the presentlydisclosed SDA system provides, presents a way to also manage essentiallyall of the many complex issues with managing IP reuse.

Considering the benefits of the presently disclosed SDA methods andsystems, here is a one stop shop, or single portal for selection,purchase, and management decisions. the result is a highly beneficialinstrument and set of processes that simplify and accelerate IP marketbenefits. by providing up-front data, system definers have technical andcost tradeoff data up-front when building new SDA designs, and are ableto ‘try before they buy.’ Also, they may manage agreements at a glanceassociated with existing and proposed IP use, and the aggregate effectsthat may have on IP provider agreements. These agreements may all may bemanaged through a common portal.

The SDA system of the present disclosure further provides tools thataggregate billing/payments and integrate and manage billing/payment,thereby accounting for IP and device owners with manufacturing and saleschannel audit data. The SDA system of the present disclosure affordssignificantly enhanced operational compatibility. The present SDAarchitecture addresses compatibility issues for design, test benches,verification, and operation of IP once integrated into a design.

Moreover, the presently shown SDA system provides database definedwrappers. Here, the SDA system generates a database use driven wrapperaround IP for integration, containing optimized mode controls,communication, wires, etc. The system presents assertions, monitors, anddebuggers. With the SDA system, an efficient monitor and debugcapability, including integration assertions, are provided that indicatewhere use problems might exist.

The SDA system of the present disclosure further provides flexibleintegration and interoperability. By default, all mode controls, datacommunication, wire connections are in-silicon configurable,automatically selectively optimized through specification or design casemining from verification. This includes holistic SDA IP support from aweb-based SDA user interface. The web-based SDA user interface providesuser support and ticket tracking, whereby IP users may obtaindocumentation, news, and update information on IP. When issues requireIP owner support, the site facilitates controlled tracked closurethrough a ticket system.

In addition, the SDA system includes a provider support portal. Theprovider support portal includes an IP provider dashboard that allows IPproviders to manage IP deployment and support for all their customerusers through a common portal, more effectively meeting customer needs.

The SDA system also provides for opportunity mining that may beassociated with the web-based interface. There, users may request new IPfunctionality. IP providers may compete for new business, and designdata may be mined to uncover opportunities to optimize new versions ofIP offerings.

The SDA system of the present disclosure represents information relatingto implementing designs in a relational database form 400-405 withcontrolled shared access and use by new design stakeholders as well assystem design automation tools 100. The SDA system incorporates apreferred multi-agent event-driven method of operation and architecturetopology that facilitates automated design generation from libraries ofmixed signal hardware and software IP. Database parameter entries formixed signal IP and designs may be in-design programmable for maximumend system flexibility, or fixed for generating optimized designs. TheSDA system enables providing a complete cloud-based collaborative systemdesign ecosystem that provides the capability for users to easily movefrom concept to new chip design and simulation using only a web browser.Additionally, the ecosystem provides a simplified holistic approach tonew design efforts.

FIG. 1 shows the web application partitioning 100 for different aspectsof performing cloud-based SDA activities performed through the site, andFIG. 2 shows SDA generated example design topology and related IP reusesockets 200 used in an automated new design build. Upon login, each useris provided information such as access, views, and progress summaries ontheir DASHBOARD 101/601 according to the needs associated with theirrole. Users may be system designers that select and utilize IP from thePLAYERS library 102/602 when building their new design 206 using theORCHESTRATE application 103/603, requirements management, verification,and test users that specify, define, and simulate application specificuse cases with the REHEARSE application 104/604, application and newsoftware developers requiring real-time FPGA emulation capabilitiesthrough the PERFORM application 105, or IP developers and providers thatuse the AUDITION application 106/605 to ensure their IP is ready forinclusion in PLAYERS 102/602 for use by ORCHESTRATE 103/603. Additionalnon-development users may utilize the SDA site 100 for supporting newdesigns, supporting PLAYERS IP, managing PLAYERS IP licensingactivities, and accessing information relating to newly created designs.Also, available from the site is COLLABORATE host OS extension anddriver SW 107 to support the use devices created through the SDA site.

FIG. 12 shows the community tasks 500 interfacing to the cloud-based SDAcapabilities 501. System design 502 would be the person initiating andbuilding new ORCHESTRATE based designs from PLAYERS based IP libraries.IP design 503 may import functions to the PLAYERS library using theAUDITION tool, or may examine specifications entered in AUDITION bySystem design 502 and respond with new IP to meet new requirements. ICdesign 504 may extract a design specified, built, and verified by systemdesign 502, or may share in the system verification effort by using theREHEARSE capability. IC verification 505 may be a shared responsibilitythrough the dashboard between all stakeholders in a new design,including IC design engineers for the final gate level verificationsimulations. All stakeholders may share the SDA produced design andsimulation engine, including IC test 506 and applying EDA support tools507. It is noteworthy to point out that each of the tasks 502-507 do notnecessarily need to be the responsibility of the same organizations, butmay be distributed and/or shared by multiple organizations through theSDA system. Additionally, the presently disclosed SDA ecosystemillustrated with web browser examples 601-605 are provided to webdevelopers through a RESTful API. The API delivers SDA portalfunctionality to outside organizations or companies so that SDA may bedelivered through the websites of those organizations, allowingvalue-add delivery and access to the common SDA portal. For example, IPdesign elements for PLAYERS may be provided by EDA, IP, or semiconductorcompanies, where the SDA system allows them all to be used together in acollaborative practical system with IP from other organizations. Also,system design may be performed by IC companies wishing to develop a newcatalog part where the useable models may be made available to their endcustomers, or by end customer that wish to define a new product fromavailable IP they wish to be considered for manufacturing, which maythen be further refined or customized to meet a broader marketopportunity.

Mixed signal IP within the PLAYERS IP library 102/212/602 are each madeup with any combination of library components such as input/output pads208, digital 209 and analog 210 circuitries, and software 211. Thelibrary 602 may be searched and browsed for determining appropriatefunctionality for a system designers project needs. IP may be simplyselected for inclusion into the desired IC design, analogous to anonline shopping experience where items are included into a cart forlater checkout.

The ORCHESTRATE SDA application 103/603 is where IP selections forintegration are made, with die size and cost estimates (with anticipatedIP license costs) may be updated and presented to the user according totheir project parameters, such as process and fab choices andanticipated optimization efforts. ORCHESTRATE 603 provides opportunitiesto further define operational parameters such as mode control settingsand registers or input data sink bindings to other IP data sourceoutputs that result in the necessary IP wrapper circuitry beingautomatically optimized for the intended use, either during theselection process or later.

As user configuration parameter data is gathered or defined, ORCHESTRATEmay provide early flags indicating potential integration issues that mayneed to be addressed, including but not limited to internal HW busbandwidth issues, target DSP or MPU software instruction cycleutilization levels, estimated power requirements, and interface IPbandwidth estimates. Some issues that arise may be addressed during thesystem automation build process, such as flagging tagged signalattributes limit conflicts, adjusting wrapper FIFO depths where present,repartitioning functional IP modules into different subsystems, addingadditional programmable core IPs when necessary, and repartitioning thedivision of SW IPs among the programmable cores. However, some mayrequire changes in user selection of IP or even require a user to defineIP that may not be currently found in the system.

ORCHESTRATE allows users to define functional requirements for new IPwhich may be sent to 3rd party IP providers for development andinclusion in PLAYERS. IP under development may limit visibility andaccess as required to meet the confidentiality needs of all usersinvolved. In the case of selecting of specific software processing cores303/304, such as DSPs, MPUs, or MCUs, may be explicitly selected fromPLAYERS by users, or ORCHESTRATE may recommend the most appropriateprocessing cores for the high-level software functions 306 selected foruse by the system design user. ORCHESTRATE automatically builds thedesign 206 and test bench 202 and user documentation.

Once PLAYERS IP 102 selection is completed and optionally configuredthrough ORCHESTRATE 103, the IP within the integrated design may beverified using simulation efficient models using the REHEARSEapplication 104, as the PLAYERS IP contain reusable self-test simulationcontrols 201, generators/monitors 203 to provide IP verification in theintegrated design without additional user activity. Additionally,advanced verification environment capabilities (i.e., using VVM or UVMmethods) may be included for reuse with PLAYERS IP for performingconstrained random verification test activities upon the integrateddesign.

These capabilities may be used with little or no user intervention, orusing some user directives through the REHEARSE interface. Also, usefulto users is the ability to use REHEARSE for specifying user directedapplication specific verification test cases that make up the designsregression list. Using the inherited reusable test bench tasks andcommands 213, users may build test cases through text based commandlists, web table interfaces, or GUI based configuration and monitoringcontrols in a schematic like environment.

A directed test case built in REHEARSE specifies the designconfiguration for data path routing and mode controls of IP and signalgenerators in the test bench, and the setup of internal and outputsignal monitors for defining expected outputs of the specifiedconfiguration. The list of directed test cases is reported along withthe tool self-test simulation results on the verification scoreboard forquickly identifying problem areas. Also, provided through REHEARSE areother viewing options of IP I/O exercise summaries and internal IP codecoverage results for self-tests, directed tests, and constrained randomtests.

The SDA auto-generated design fabric and auto-generated IP wrappers 207shown implement the preferred multi-agent event-driven method ofoperation, where output from IP is presented to the fabric in anidentifiable manner, such as a source-based broadcast. The fabricprovides all source output communication to all IPs within thesubsystem, and sink inputs to IPs are configured to grab the datadesired when observed. This method of operation allows communicationbetween IP tools to remain loosely coupled, allowing data pathrelationships to be defined by parameters in the database andautomatically implemented as fixed or configurable circuits within theauto-generated IP wrappers.

IP wrappers also implement the multiplex selection of wire events fromother IPs as necessary, as well as configurable mode control registersrequired by IPs represented in the database that may be optimized asnecessary for the design's intended purpose. Together, theimplementation provides a hardware interface multi-agent event-basedoperating system that functions in a ‘configure and let it do its thing’principle.

The SDA system provides an integration backbone 301 that provides IPsockets that PLAYERS IP 302/310 are simply plugged in to. Theintegration backbone contains a control handler that providesconfiguration control, traffic arbitration, event routing and handling,subsystem bridging, debug port, design for test (DFT) support circuitry,clock and reset control, power management, or any other system functionsthat may be provided for the user but optionally hidden under the hoodto simplify SDA IP integration and verification.

PLAYERS IP 102/212 tools may contain any combination of socketcomponents, including functional software IP tools 306 intended tooperate within a programmable hardware MPU, RISC, DSP, or other core303/304 requiring an OS 305 to provide integration sockets for SW IP.Like the SDA fabric 301, the core processor OS implements a multi-agentevent-driven method of operation based on a configure and let runprinciple as illustrated 350. The method means that SW IP components mayobtain their input from any HW or SW IP in the system, and provideoutput for use by any other HW and SW IPs through configuration.

HW IP wrapper 351 is auto-generated with input sink FIFO 352 thatcollects desired input bus traffic for SW IP inputs. The multi-agentevent-driven operation means that sink traffic may occur at any time andat any order. One of the tasks for SDA OS 354 is to receive and separatethe sink FIFO 352 data into separate channel input queues 356 for use bySW IP sockets.

As shown, input queue 0 is reserved for communication with the SDA OSfor configuration operational purposes, such as SW code uploads,initializing SW IP mode settings, prioritizing SW IP execution, statusmonitoring, and other under the hood functional requirements of thecore. Software IP 355 inputs obtain their inputs from any input queues356 or output queues 357, and provide their output to output queues 357that may also provide data to the SDA fabric through the IP wrapperhardware FIFO 353.

In some cases, it may be desirable for some systems to integrate aprogrammable core without an SDA OS, such as the M0/M3 core example 302.In this case, the HW IP wrapper bridge greatly simplifies data transferwith the entire SDA system IPs and integrating the core within thesystem.

FIG. 5 further illustrates the base SDA OS functionality 380, where anidle loop 381 monitors cycles for comparing to continuous time counter382 that may control programmable core voltage and core operationalfrequency 383. By detecting unused idle cycles, the core voltage andoperational core frequency may be lowered to save power, or increasedwhen necessary to increase performance.

Idle loop operation is interrupted when HW interrupt events occur orinput data is present for SW IP processing to occur. Shown are threetiers of interrupt processing, tier 1 being reserved for low-prioritybackground tasks 385 and tier 3 being reserved for high-prioritylow-latency tasks 387. Socketed SW IP tools may be independentlyregistered for their required priority 385-387 to minimize dataflowproblems within the system.

The socketed backbone provides interconnectivity integration of IP, andloosely coupled operational relationships for IP input and outputprovides operational integration through the configuration of backboneand IP wrapper parameters. FIG. 4 illustrates how integrationoperational backbone parameters may be represented in a database formusing the illustrated database schema of operational parameters 400.With this approach to defining system integration and operation, designand verification efforts are simplified and may be simply definedthrough tables manipulated with a web interfaces, facilitating SDA.

USERS 401 represents the login to the DASHBOARD 101, providing userspecific information regarding the use of the AUDITION 106/402, PLAYERS102/212, ORCHESTRATE 103/403, REHEARSE 104/404, and PERFORM 105/405 webaccessible portions of the cloud-based SDA ecosystem 100. WithinAUDITION 402, the parameters that define the configuration of thewrapper to bind connections and operations to an embedded IP arerepresented. ORCHESTRATE 403 includes the PLAYERS for each design andthe further post integration attributes for the use of the IP within thedesign.

REHEARSE 404 includes the simulation control and expected behaviors foreach use case scenario of an ORCHESTRATE design. PERFORM 405 providesthe additional information required to drive the design into an FPGAbased configuration for emulation.

Following the completion of using REHEARSE 104 to build and verify thedesign, the configuration data 404 from directed use cases may becollectively analyzed to drive automated optimizations for the finaldesign, selectively and optionally removing IP configuration circuitrynot required. For example, each input of an IP may be configured toreceive source data or signals from any available IP output, but if anIP input is known to only require data from one or a few sources theremay be no reason to include the additional operational flexibility. Or,if an IP has mode controls for a variety of operational settings, thosemode controls may be optionally reduced to include only the flexibilitynecessary in the end design. In such cases, the optimization wouldrequire the changing of an IPs programmable register map or IP datawrapper used to integrate to the SDA backbone.

REHEARSE 104 will work with ORCHESTRATE 103 to make the designoptimization modifications, regenerate the user documentation, modifythe regression run test case controls, and re-verify the optimizeddesign. Optimized subsystem designs may then be introduced into PLAYERSlibrary as a subsystem for further reuse by others if desired.

The SDA system also makes provisions to provide FPGA emulationcapabilities of new designs, allowing designs to operate in real timeand interact with real world elements. This service is provided byPERFORM 105, an FPGA validation engine that may have a variety of formsincluding a server-side FPGA emulation platform, an appliance that maybe provided to the user for use on a client lab bench, or an FPGA boardthat may be suitable to be embedded within an OEM product.

For server side PERFORM 105 capabilities, the reusable PLAYERS IP102/112 contain test bench elements that make use of synthesizablesignal generator and monitoring circuits 204 that may be embedded withinthe FPGA build 202. Control of these models are identical to theverification controls that drive REHEARSE verification activities,allowing REHEARSE verification activities to be easily validated inhardware. Additionally, analog IP 210/212 such as ADCs, DACs, PGAs,mixers, and other functionality may be implemented in PLAYERS withdigital synthesizable models to be included in the FPGA emulation build.For example, an analog delta-sigma ADC clocked modulator may beimplemented as an equivalent DAC modulator, with input data coming froma parallel digital data word rather than an analog wire.

The digital representation of the signal may be provided from an I2Sinterface along with a digital interpolation filter that may be includedin the FPGA when using emulation for validation. The corresponding testbench signal generate may use types such as Verilog representations forREHEARSE, but be synthesized to provide a digital representation througha serial interface when used by PERFORM. Additionally, with server-sideFPGA capability, a USB dongle for signal I/O transfers may be madeavailable to users with signal transfers from a client bench to theremote server performed through a common internet interface.

Signal capture capability may be used to drive input stimulus toREHEARSE simulations as well. For users requiring improved latencybetween their bench and the FPGA emulating the design, an FPGA appliancemay be made available that works with a client version of the PERFORMinterface, allowing direct input to the design from external benchsources through the utilization of multiplexers place at 205 thatbypasses the synthesized signal generators.

The COLLABORATE universal software driver and operating system extension107 provides additional capabilities to designs built using SDA. IPtargeted to interface with host processors will require host driversoftware. The COLLABORATE layer is an abstraction layer that mitigatesdifferences in hardware between the IP and the host processor, allowingthat driver software to operate directly with the IP withoutmodification.

The IP driver plugs into the COLLABORATE layer, and through that layercommunicates with the IP regardless of how the host processor isconnected to the presently disclosed solution. COLLABORATE tunnelsthrough physical connections such as SPI, I2C, PCI Express, but also maybe used when the host processor is embedded within the presentlydisclosed design and connected directly to the presently disclosed bus.

COLLABORATE may also be used to communicate across network boundaries,allowing the customer to write software and test it using REHEARSE andPERFORM services. COLLABORATE also provides sockets for IP evaluationsoftware, further extending IP reuse into the host past the driverinterface.

The SDA system includes extending the method of operation using eventdriven operations for backbone operational integration onto protocolsfor standard user interfaces that utilize identifiers for broadcast datatransfers. This allows users to configure the part to know whatinformation they are interested in, and then the information coming toan external host in an identifiable way when information is broadcasteliminating the need to actively extract data in response to interrupts.Another benefit is the standardization of the extensible and flexiblehost driver.

Once the SDA site is used to complete the high-level design andverification, the design is ready for use in a system for FPGA use, ormay be handed off to silicon manufacturers or providers to complete thebackend flow and realize a final product for the system design user. Itis important to realize that the SDA system is also capable to providebenefits to automate much of the back-end flow effort as well. Forinstance, PLAYERS IP 212 may contain reusable backend support scripts216 for streamlining tasks such as logic synthesis and timing closure,physical layout blocks 217, performance test program and patterngeneration scripts 218, or even the actual test program data 218 for anIP if the IP was not touched and further optimized since its last use.

FIG. 18 shows a subsystem bridging example topology 1000, where SoC #1illustrates subsystems A 1001, B 2011, and C 1041 networked throughauto-generated bridge subsystems 1021/1031, as well as networked to SoC#2 through IP named SPI w/SDA Protocol 1043/1053. The example embodimentuses a subsystem Handler IP 1002/1012/1022/1023/1042/1052 that includesan optional bridge for interfacing to another subsystem's Bridge IP.

Handler 1002 may be configured for transferring specific designsubsystem A 1001 source broadcasts to bridge subsystem 1021 throughbridge IP 1023, where the source based address will be translated to abridge IP 1023 source based address. Using this scheme, a single outputfrom any IP source in the entire system may be used by by one or more ofother IP sink inputs on one or more design subsystems within SoC #1.

If an interface IP, such as the SPI w/SDA Protocol 1043/1053, mayinclude a tagging mechanism to identify data, data routing may continueacross chip boundaries, allowing any IP to gain input from any other IPwithin the entire distributed system. This method of operation providesan inherent NOC that may self-manage data flow and also operate as aNBC.

When combined with configurable sink listening registers in the SDA IPwrappers, designs include all the hooks necessary to monitor and extendfunctionality off chip. Additionally, when applying artificialintelligent (AL) machine learning (ML) to existing system operations,any relevant data within the entire NBC system may potentially be usedby simply adding AI ML functionality throughout the system. Since all HWor SW socketed IP functions operate in a loosely coupled fashion, robustand flexible overall system operation is realized, includingdisconnecting and/or dynamically changing component makeup on the flyduring system operation.

Design database parameters may be implemented as in-system configurablewith operational bounding to allow AI engines to adapt system behavior.Additionally, mission critical and safety related system designs forapplications such as autonomous driving vehicles or medical relateddevices may easily implement IP with health check monitoring andreporting, broadcasting status to reporting and failsafe system controlmechanisms.

In light of the above description, the following provides a descriptionof the use of the SDA system of the present disclosure. The descriptionbegins identification of a use provisions table as appearing in FIGS. 19and 20. The delivery of SDA capabilities as described in the SDA systemprovide all stakeholders of a new SoC/ASIC/FPGA design developmenteffort a common interface to efficiently collaborate on the commonproject effort. Shown in the table of FIGS. 19 and 20 are some examplesof respective roles, and what the delivery system of SDA is able toprovide for each. Normally, the user roles are organizationallyseparated with the tasks and workflow of each responsibility beingpartitioned away from other roles, making practical collaborationdifficult. Shown in FIGS. 19 and 20 are how SDA database driven designmay positively impact each stakeholder's role.

The presently disclosed SDA system may be implemented utilizing standardcomputing hardware and standard and custom software packages using acomputing server as the base hardware. The server hardware consists ofprocessor, memory, hard disk storage, and network connection. Theprocessing power and memory combination should be adequate in order toprovide computational and information queries, as well as handle the webservices for multiple users at a time. The hard disk space should beadequate to contain the core database, web files, and temporaryworkspace for the designs and simulations. The server used for theimplementation of the current SDA system utilized four, quad-coreprocessors, 48 GB of memory and two 500 GB hard disks. The softwarecomponents described below operate on the previous described hardware toachieve the implementation of the SDA system. The software componentsbelow describe SDA system components that are standard availablecomponents, not customized by Presently disclosed.

An exemplary server operating system may provide the necessarycomponents, include (1) The Make build system, (2) GCC/G++ compilertoolchain, and (3) Chroot. The Make build and GCC/G++ compilertoolchains are used to build the simulation program component of the SDAsystem. The Chroot functionality confines the simulation program toprevent hostile components from affecting the larger system. Thisfeature locks the simulation in a proxy-system which prevents the mostmalicious behaviors. For the purposes of this SDA architecture, GentooLinux was chosen to meet the above criteria.

The web server software should execute active/scripted content necessaryto provide database driven form content to the user. Presently discloseduses PHP to provide server-side active content to the user, andJavaScript to provide client-side active content. For the described SDAsystem, Apache web server is used for the web server implemented on theserver.

The SDA system uses a server database at the core to store and manageinformation provided by the user and source the information back to theuser and various process/programs that make up the SDA system. There areseveral options for SQL databases that all provide similar options andfeatures. To meet the above criteria and implement the revision systemused in the SDA system, the PostgreSQL database is used.

Version control software is utilized in the SDA system to record thechanges and maintain a history of the files that make up theintellectual property code used in design tools and system designs. Itprovides the ability to track changes and recall previous versions ofthe files that would not be available without the versions control inplace. Version control is achieved for both the upload and downloadaspects of the SDA system. Git version control software is used in theSDA system to satisfy the version control component of the SDA system,such as providing a container for an IP, and a design compilation buildcontainer that allows access to executable simulation code and REHEARSEsimulation scripts.

In order to compile the System Verilog code into C++ code for simulatingthe system designs created in the SDA system, a compiler must beutilized. Verilator, a free software tool, is utilized in the SDA systemto achieve the desired form of simulation system that may provide dataacross a web socketed connection.

In order to access the information store in the database and interactwith the various processes of the SDA system, a user interface isrequired. The user interface must provide user input, validation,feedback, and display results/information from the SDA system and itsprocesses to satisfy the needed functionality. While a compiled softwareinterface meets the user interface requirements, a web-interface waschosen to negate the need of the user to install software to theirpersonal computer/device. To implement the web-based user interface, theBootstrap framework was utilized to implement the web-pages and displayalong with custom JavaScript and PHP code.

The software components below describe SDA system components that arecustomize developed software components by presently disclosed SDAsystem. As previously described, the user interface is required toprovide user input, validation, feedback, and displayresults/information from the SDA system. To implement the web pages usedto achieve the user interface, JavaScript and PHP programming code areutilized in the design of the user interface page. They connect to theAPI to display and collect data to/from the user and transmit user datato the API.

To exchange data with the database, an API is implemented for this SDAsystem. It allows for the connection of various programs to the databaseinformation in a controlled and consistent methodology.

The WebSocket server provides a connection between the design simulationand user interface components of the SDA system. The WebSocket server isrequired to authenticates the user, start simulation processes, andtransmit simulation commands and data. The WebSocket server uses theNoPoll library in order to manage the web socket connections.

In order to provide design simulation, the SDA system must compile thesystem design code into a complete simulation program. The simulationcompiler previously described, does not generate a complete program andtherefore custom wrapper code was written to complete this action. Thecustom wrapper code additionally integrates a TCL library to provideexecution of scripts in the final simulation program. The wrapper codecould just as easily incorporate other scripting libraries such as Perlor Python as well.

Presently disclosed SDA system provides for the design of completesystems from reusable design block/tools. These tools are combinedtogether with system specified parameters to achieve the final systemdesign. To compile the tools into the final design, multiple scriptswere written manage the creation of files or create individual files.The generation scripts create the chip design that may be processed withVerilator to create a design simulation or download as the designend-product code.

In order to achieve protection of customer design tools and systems andproperly log and retrieve data from the database, the SDA system mustprovide proper authentication of the user, such as an ApachePlugin-PostgreSQL Authentication Module. An Apache server plugin toolwas written to provide authentication of users accessing Git over HTTPand HTTPS. This provides required security for intellectual propertyserved via the Git revision control system.

In use, SDA system coordinates the use of the DASHBOARD, AUDITION,PLAYERS, ORCHESTRATE, and REHEARSE tools as follows. DASHBOARD servesfor communication, advertising, and support, as well as provides focussite access for all of the SDA system. The AUDITION tool provides IPDefinition, specifications, specifications, import and managementfunctions in providing for IP management. The PLAYERS tool presents anIP library to provide IP information & access. The ORCHESTRATE toolprovides design definitions, specifications, and management, inproviding design management functions. The REHEARSE tool provides designcompilation and simulation to enable design generation and simulationservices.

With the functions these tools perform, there are services of importanceaccording to the roles of the various SDA system users. Here, thevarious users include system designers, project managers, IC/FPGAdesigners, IP designers, verification engineers, validation engineers,DFT engineers, back-end flow engineers, application engineers, IPproviders, semiconductor suppliers, and system suppliers.

System Designers set top-level specification and high-level design ofnew systems, SoC devices, and FPGA based designs. Project Managersmanage the design development progress. IC/FPGA designers handle designand implementation of tangible semiconductor based products that maycontain a combination of digital and analog circuitry and embeddedsoftware. IP designers take care of design and implementation of mixedsignal tools for use within designs and systems. Verification Engineersare responsible for ensuring designs reliably meet their intendedpurpose before being released to build. Validation engineers aresponsible for ensuring designs operate as required within the systemsthey are intended for. DFT engineers handle “Design for Test” activitiesto provide implemented features that ensure new products are screened toensure quality on shipment. Back-end flow engineers take care ofsynthesis, layout, timing closure, mask prep, etc. to bring designs frommixed signal simulation to buildable product. Application engineersprovide product support for applying new devices to particular customerand application needs. IP providers are businesses for providing IP tosemiconductor designers/suppliers. While, semiconductor suppliers arebusinesses for providing semiconductors to system designers/suppliers.And, system suppliers are businesses for building and shipping productsthat use semiconductor SoC/ASIC/FPGA devices.

For system designers, the DASHBOARD enables collaboration on new productdevelopment opportunities and proposals. The DASHBOARD further makespossible managing competitive IP and design development efforts,communicating with all new device stakeholders, and tracking/reportingproject development status. For system designers, the AUDITION toolcollaboratively capturing/documenting customer mixed signal IPrequirements, providing C/C++ behavioral IP prototyping, and sharing IPneeds with IP designers and providers. The PLAYERS tool permits systemdesigners to browse visible IP and designs, organize interesting IP intopersonal lists, and obtain IP for use in designs. The ORCHESTRATE toolsupports system developer efforts to define and document new conceptualdesigns, specify collective operation system specifications, sharedesign definitions with other project stakeholders, and make rapiddesign spins/modifications. The REHEARSE tool supports system designersto quickly generate automated builds of highly flexible and configurableproof of concept and prototype designs, share simulations with otherproject stakeholders, and simulate quickly with inherited IP task/testscripts.

For project managers, the DASHBOARD enables communication with all newdevice stakeholders and tracking/reporting project development status.The REHEARSE tool supports project managers to track and manage designsto meet all of technical requirements and specifications.

For IC/FPGA designers, the DASHBOARD enables managing technicalalternatives with system and IP designers, and communicating with otherdesign stakeholders and IP providers, as well as tracking/reportingdesign development status. For IC/FPGA designers, the AUDITION toolprovides access to IP details when necessary and allowed by IPproviders/owners, as well as provide design related information to IPproviders for others to use. The PLAYERS tool permits IC/FPGA designersto browse visible IP alternatives for designs and obtain IP for use indesigns. The ORCHESTRATE tool supports IC/FPGA designers' efforts toobtain usable definitions from system designers, as well as to furtherdefine IP and design relationships for automated optimization of designintegration circuitry. In addition, the ORCHESTRATE tool supportsIC/FPGA designers' efforts to optimize system partitioning and IP formfor operational optimization.

The REHEARSE tool supports IC/FPGA designers to quickly generateoptimized automated builds of final designs suitable verification andback-end flow task handoff. In addition, the REHEARSE tool supportsIC/FPGA designers to write targeted simulation test cases for functionaldesign review and sign-off, as well as to share simulations with otherstakeholders as necessary to facilitate quick problem resolution.

For IP designers, the DASHBOARD enables obtaining IP requestopportunities and providing technical support to all IP users. TheDASHBOARD enables communications with IP information to all IPstakeholders, as well as the ability to track/report IP developmentstatus.

For IP Designers, the AUDITION tool allows obtaining new IPdescriptions, specifications, and requirements, as well as to upload newand existing digital/analog circuit designs and/or embedded softwarefunctions with required test bench support. For IP Designers, theAUDITION tool provides technical updates and tiered access to others asneeded, conditioned upon whether there is necessary permission provided.

The PLAYERS tool permits IP Designers to release and make IP availablefor use in designs, as well as protect IP details, allowing options forothers to use IP without exporting IP. The ORCHESTRATE tool supports IPDesigners efforts to create test designs for verifying IP operation inauto-built SDA based systems, as well as to provide test designs forevaluation by prospective users.

The REHEARSE tool supports IP Designers to simulate IP to ensure properfunctionality, as well as share technical simulation builds forevaluation by others and mixed signal simulation scripts for use bySystem and IC designers.

For verification engineers, the DASHBOARD enables tracking/reportingverification development status. For verification engineers, theAUDITION tool provides IP mixed signal test benches and inheritsin-system IP test scripts, as well as automated scoreboardspecification/feature inheritance functions. The ORCHESTRATE toolsupports verification engineers' efforts to uses designs with mixedsignal test benches, while inheriting integrated verification envelopesand functional constraints. The REHEARSE tool further supportsverification engineers to quickly generate automated builds of coreassertion based designs, test benches, and IP access tasks, as well asshare mixed signal test cases for review by design.

For validation engineers, the DASHBOARD enables tracking/reportingproject development status. For validation engineers, the AUDITION toolprovides IP functional FPGA ready test benches and permits applyinginherited simulation IP test scripts to emulation and siliconevaluation. The ORCHESTRATE tool supports validation engineers' effortswith functional FPGA ready test benches and design, providing emulationcapability with common simulation scripting environment. The REHEARSEtool supports validation engineers with a REHEARSE script interface toperform FPGA emulation running on server or client bench. This has useto validate same verification scripts from REHEARSE running emulateddesign or final silicon design.

For DFT engineers, the DASHBOARD enables communication with all newdevice stakeholders, as well as tracking and reporting projectdevelopment status. For DFT engineers, the AUDITION tool provides acommon IP wrapper interface with DFT features to standardize DFT flow,as well as options to extend DFT reuse to IP based vector sets. TheORCHESTRATE tool supports DFT engineers' efforts with a common DFTinterface for IPs through SDA Fabric allowing streamlined DFT flow.

For back-end flow engineers, the DASHBOARD enables tracking andreporting back-end development status. The AUDITION tool providesback-end flow engineers placeholders for modularized backend toolscripts for reuse after design handoff. The ORCHESTRATE tool alsosupports back-end flow engineers' efforts with automated integrationfabric provides standardized clock, power, operational timing,architecture to streamline backend flow.

For application engineers, the DASHBOARD enables tracking and reportingcustomer support issues for designs and their used IPs. The AUDITIONtool provide application engineers with updates for future uses of IPthat address in-field issues. The PLAYERS tool permits applicationengineers to easily upflow to system and IC designers to incorporateissue fixes in future parts. The ORCHESTRATE tool also supportsapplication engineers' efforts with automated user documentationgeneration. The REHEARSE tool supports application engineers to quicklygenerate builds suitable for FPGA based pre-release evaluation systems,or FPGA based benches for final silicon evaluation tools.

For IP providers, the DASHBOARD enables tracking and reporting the useand support of IP and the auditing and billing of IP customers, as wellas new IP opportunity mining. For IP providers, the AUDITION tool allowsIP use without providing IP details. The PLAYERS tool supports IPproviders' efforts to advertise IP for use. And, the REHEARSE toolsupports IP providers to provide browser IP simulation for evaluation.

For semiconductor suppliers, the DASHBOARD enables tracking andreporting use and support of used IPs, even from different vendors, aswell as tracking and reporting auditing and royalty payments. Thisincludes single payments with the SDA system of the present disclosuremanaging IP vendor payments. The DASHBOARD also supports new deviceopportunity mining.

For semiconductor suppliers, the AUDITION tool manages internal IP andensures external IP compatibility. The PLAYERS tool permitssemiconductor suppliers to advertise needs for IP. The ORCHESTRATE toolsupports semiconductor suppliers' efforts to automatically generatehighly flexible and extensible designs, as well as to involve outsidersto collaborate with your design flow. The REHEARSE tool supportssemiconductor suppliers with browser design simulation for evaluation.

For system suppliers, the DASHBOARD enables⋅Track/report support of bothdevice designs and the IP within them, regardless of providers.

A technical aspect of the present disclosure includes providing methodsand systems for SDA of mixed signal electronic circuitry includingembedded software designs for creating ASICs, sub-systems, and SoCs. TheSDA system described extends IP reuse beyond the circuit and stand-aloneverification capabilities that are common practice today which limit thebenefits of reuse. By solving the integration problem first in a looselycoupled manner, complex mixed signal SoC devices may achieve higherlevels of IP reuse with push button ease through the cloud,significantly improving time to market, design resource limitations,risks for first time silicon success, and the tasks of managing businessmultiple relationships of IP providers. SDA generated designs use amulti-agent method of operation, creating powerful and flexible designsthat provide both NOC and NBC for distributed system operation, andenhanced non-intrusive in-system monitoring for mission critical andsafety related applications. The method of operation also easesintegration of AI and ML functionality.

Another technical aspect of the present disclosure includes methods andsystems for SDA of mixed signal electronic circuitry including embeddedsoftware designs that enable the system developer to build and simulatenew designs in minutes using SDA. The disclosed subject matter providesprograms and/or scripts that automate the generation wrappers fromsystem integration database entries for mixed signal circuitry andsoftware IP tools. The presently disclosed methods and systems providemethods of operation able to present outputs in an identifiable mannerand implement configurable or fixed input select control circuitry orsoftware for tool inputs. From this derives assembling the tools as asystem through a NoC (Network on a Chip) and software OS implementation.The present disclosure, thus, provides programs and/or scripts thatcompile the generated design and test bench, and execute inheritedsimulation stimulus and self-checks from the IP tool containers.

The disclosed configuration architecture allows this to be eitherinherited IP script or database driven. Here it is convenient tosystematically collect and store wrapper simulation data so that it maybe analyzed and drive database entry optimizations for a design based onthe way it's used in verification. Script based testing capabilities aresynergized so the same scripts may be used to operate Rehearsesiulations for verification or Perform emulations for validation.

The disclosed subject matter also provides relational databasefunctionality. Here, mixed signal circuitry and/or software tool designfiles are organized, stored, as IP containers and accessed using aversion control system such as Git (/git/) in a usable form foraccomplishing SDA. This SDA system provides a common integration andmethod of use allowing systematic implementation for all aspects of IPreuse that may be represented in database form from the container, andworking with the relational database and code generators.

Yet a further technical aspect of the present disclosure includes asystem architecture whereby data and signals may be flowing betweenmixed signal hardware or circuitry and/or software tools, which may beimplemented with IP source identifiers (source-based addresses, indexes)so that tool inputs may be obtained through configuration selectsimplemented in HW IP or SW IP wrappers, and further so thatconfiguration information may be represented in a relational databaseform. Configuration selects are implemented as system user configurableor fixed configuration settings from the database. Source identifiersmay be kept as absolute (unchanged) or relative (modified as it flowsthrough connected subsystems). Integrated operation is accomplished as a“configure input selects and let it work” manner.

A yet further technical advantage of the presently disclosed subjectmatter includes the ability to support a cloud-based collaborativeenvironment. The subject matter here disclosed requires no softwareinstallation. Using a cloud-based shared environment for allstakeholders of a new design effort, the present SDA system provides acloud-based IP tool for representing IP in a database form thatfacilitates automation. The cloud-based IP tool here disclosed managesall IPs owned/controlled by a user/group for design, support, and/orbusiness management. The presently disclosed cloud based design toolenables defining a design and an associated test bench, including the IPthat the design uses and the configuration of each of the employed IPtools. Still further, the cloud-based environment here provided enablesa cloud-based simulation tool for verifying circuitry and software mixedsignal designs.

The detailed description set forth herein in connection with theappended drawings is intended as a description of exemplary embodimentsin which the presently disclosed subject matter may be practiced. Theterm “exemplary” used throughout this description means “serving as anexample, instance, or illustration,” and should not necessarily beconstrued as preferred or advantageous over other embodiments.

This detailed description of illustrative embodiments includes specificdetails for providing a thorough understanding of the presentlydisclosed subject matter. However, it will be apparent to those skilledin the art that the presently disclosed subject matter may be practicedwithout these specific details. In some instances, well-known structuresand devices are shown in block diagram form in order to avoid obscuringthe concepts of the presently disclosed method and system.

The foregoing description of embodiments is provided to enable anyperson skilled in the art to make and use the subject matter. Variousmodifications to these embodiments will be readily apparent to thoseskilled in the art, and the novel principles and subject matterdisclosed herein may be applied to other embodiments without the use ofthe innovative faculty. The claimed subject matter set forth in theclaims is not intended to be limited to the embodiments shown herein,but is to be accorded the widest scope consistent with the principlesand novel features disclosed herein. It is contemplated that additionalembodiments are within the spirit and true scope of the disclosedsubject matter.

We claim:
 1. A system, comprising, a plurality of integration componentsfor the functional integration of a plurality of digital, analog, and/orsoftware Intellectual Property (IP) functions through configurationsettings where the IP functions remain autonomous and loosely coupled;data output values including source identifer information and datainputs with a plurality of data input sink selections to provideconfigurable data routing.
 2. The system of claim 1, further comprisinginstructions for providing both hardware and software IP socketssuitable for IP functions to be interchangably represented in either ahardware or software form.
 3. The system of claim 1, further comprisinginstructions for generating system components for collecting wire eventoutputs from said IP sockets with selection controls for distributed useof wire event inputs to said IP sockets.
 4. The system of claim 1,further comprising of generating system components for providing clock,reset, and/or power management control of IP sockets.
 5. The system ofclaim 1, further comprising of generating system component for providingIP socket monitors and stimulus accessible with a debug port.
 6. Thesystem of claim 1, further comprising of mode control configurationcontrol for providing the integration control of IP inputs and outputs.7. The system of claim 1, further comprising of enable features fordynamically changing the operational makeup of the system duringoperation.
 8. The system of claim 1, further comprising of bridge and/orinterface hardware that provides unlimited configurable extensibilitybetween IP functions between subsystems within and/or beyond a chip. 9.The system of claim 1, further comprising of customizable integrationfabric without requiring changes to the IP modules used.
 10. A method,comprising the steps of: providing a web browser accessible dashboardfor system design stakeholders according to their project roles;providing a web browser tool interface for entering information definingan IP function, interface, and access control information to provide acontainer for importing the design information relating to the IP;providing a web browser dashboard that provides a consolidated IPmarketing and support site for IP owners; and providing a web browserdashboard that provides a consolidated IP licensing management site forIP customers.
 11. The method of claim 10, further comprising the step ofproviding of a web browser accessible database catalog of SDA-ready IP.12. The method of claim 10, further comprising the step of providing aweb browser tool interface for selecting and configuring IP modules, anddefining acceess control for SDA functional integration of a system. 13.The method of claim 10, further comprising the step of providing of aweb browser accessible simulation of a compiled SDA generated design andtest bench.
 14. The method of claim 10, further comprising the step ofproviding a web browser accessible FPGA emulation of a compiled SDAgenerated design and test bench.
 15. A method for system designautomation (SDA) of mixed signal electronic circuitry and software,comprising the steps of: generating a networked plurality of mixedsignal circuitry and software sockets for instantiating from systemintegration database entries for mixed signal circuitry and softwarefunctional IP module blocks, further comprising the steps of: presentingevent wire and communication data outputs of hardware and softwarefunctional IP with identifiers according to output web-accessibleinterface; implementing configurable input select control circuitryand/or software for providing inputs of hardware and software functionalIP using event wire and communication data output identifiers accordingto a web-accessible interface; implementing configurable mode controlregisters, memory contents, and/or parameters for providing functionalIP module block functional modifiers according to mode web-accessibleinterface; assembling said mixed signal circuitry and software wrappersinto an SDA generated design using a combination of network on a chipand/or software operating system and/or network beyond a chip to allowfunctional IP modules to operate together as a system; organizing andstoring said mixed signal circuitry and software IP module design filesinto IP containers; and accessing said IP containers using apredetermined version control software system; and providing said IPincluding test bench and verification components for providing stimulusand monitoring IP functionality during operation.
 16. The method ofclaim 15, further comprising the step of a generated primary firstsystem and a second test bench system for functionally verifying IPincluded in primary first system.
 17. The method of claim 15, furthercomprising of the step of providing said IP including test bench andverification components for providing stimulus and monitoring IPfunctionality during operation.
 18. The method of claim 15, furthercomprising the step of a generated primary first system and a secondtest bench system for functionally verifying IP included in primaryfirst system.
 19. The method of claim 15, further comprising the step ofemulating both generated systems within a FPGA for functional real-timevalidation.
 20. The method of claim 15, further comprising the step ofuniversal driver software to interface to SDA generated designs usingloosely coupled configurable data routing.